Often, a computer system includes a controller, such as a micro-processor, and one or more memory chips, such as random access memory (RAM) chips. The RAM chips can be any suitable type of RAM, such as dynamic RAM (DRAM), double data rate synchronous DRAM (DDR-SDRAM), graphics DDR-SDRAM (GDDR-SDRAM), reduced latency DRAM (RLDRAM), and pseudo-static RAM (PSRAM). The PSRAM is usually based on DRAM and provides significant advantages in density and speed over traditional static RAM (SRAM).
Typically, a DRAM includes one transistor and one capacitor memory cells arranged in one or more arrays of memory cells, which are arranged in memory banks. Conductive word lines, referred to as row select lines, extend in one direction across an array of memory cells and conductive bit lines, referred to as digit select lines, extend in another direction across the array of memory cells. A memory cell is located at each cross point of a word line and a bit line.
The DRAM includes one or more row decoders, one or more column decoders, and sense amplifiers. The sense amplifiers can be differential sense amplifiers, wherein each sense amplifier receives one bit line at each of two differential inputs. To read or write memory cells, the DRAM receives a row address, a column address, and control signals, such as row address select (RAS) and column address select (CAS) signals. A row decoder receives the row address to select a word line or row of memory cells and the row address is latched into the row decoder via the RAS signal. A column decoder receives the column address to select one or more bit lines or columns of memory cells and the column address is latched into the column decoder via the CAS signal. Memory cells at the intersection of the selected row and the selected columns provide data bit values.
At the sense amplifiers, one of the bit lines receives a data bit value from a selected memory cell and the other bit line is used as a reference. To read the data bit, the sense amplifier amplifies the difference between the data bit value and the reference value and provides a sensed output value to an output driver. To write a data bit into a selected memory cell, input drivers overdrive the sense amplifier. One input driver overdrives a data bit value onto the bit line that is connected to the selected memory cell and another input driver overdrives the inverse of the data bit value onto the reference bit line.
A DRAM chip receives a supply voltage, such as VDD or Vint, and a reference voltage, such as VSS or ground, from external circuitry. In addition, a DRAM may internally generate several other voltages. Some of these internally generated voltages are regulated out of the supply voltage and some of these internally generated voltages are pumped or boosted out of the supply voltage for a voltage that is higher than the supply voltage and out of the reference voltage for a voltage that is lower than the reference voltage.
Some DRAM chips internally generate a negative word line low voltage (VNWLL) and a negative back bias voltage (VBB). The VNWLL is a negative voltage provided on word lines to turn off memory cell transistors. VNWLL reduces or prevents sub-threshold leakage from the memory cells. VBB is a negative back bias voltage applied to the p-wells of the memory cell transistors. VBB suppresses sub-threshold leakage of memory cells and fine tunes the threshold voltage of memory cell transistors.
In some DRAM chips, one bit line contact is coupled to two memory cell transistors. One of the two transistors is controlled via one word line to access one capacitor and the other transistor is controlled via another word line to access another capacitor. If the channel lengths of the two transistors are different, the transistors will have different threshold voltages and different sub-threshold leakage characteristics. Providing VNWLL to the two word lines and each of the two transistors may lead to leakage from one or both of the capacitors, which results in loss of data from the memory cells.
For these and other reasons there is a need for the present invention.